A sensor is a transducer plus an analog front end plus an analog-to-digital converter plus a stream of bits aimed at a downstream processor. Most of those bits never carry meaning. Substrate primitives — joint-distribution storage, library-based pattern recognition, signed provenance — map onto silicon shapes that already exist (content-addressable memory, embedded crypto, low-power compute-in-memory) and can live on the sensor die itself. The wire leaving the package carries decisions and signed records, not raw samples.
Validiti owns the substrate architecture and the on-die coordination IP. The semiconductor industry owns the fabrication, the analog front ends, the packaging, and the physics of the transducer itself. The architectural match is published here for the field to evaluate. License terms favor research collaboration with the federal program offices and the sensor IC and MEMS foundry community.
Validiti does not own a fab, does not design analog front ends, does not package or test silicon, and will not. The shape of this engagement is closer to a Bell Labs preprint than to a commercial roadmap.
Modern sensor systems push raw samples down a wire to a host, where a CPU or accelerator runs pattern recognition and an application acts. Several costs accumulate along that wire:
| Cost source | Magnitude | Why moving substrate to the source addresses it |
|---|---|---|
| Bandwidth carrying samples that mean nothing | 10×-1000× | The library decides at the source. Only signed decisions and rare-rows leave the package. |
| Energy spent moving bits, not computing them | ~60% typical SoC | On-die joint-distribution lookup is a CAM read; no off-die transfer required. |
| Latency from sample to decision | 100µs-10ms | Sub-microsecond decision at the sensor die. Bus and host scheduling no longer in the loop. |
| Provenance and chain-of-custody gaps | Structural | Embedded crypto on the same die signs the row at the moment of capture. |
| TinyML model retraining and drift | Per deployment | Library updates as signed rows; no retraining, no model swap, no fine-tune step. |
The substrate is not asking silicon to do something it struggles with. It is asking silicon to do exactly what it already does, in a coordination shape that current architectures do not deploy on the sensor die.
A multi-channel joint row is a wide content-addressable key. The library is a CAM array with frequency-ranked entries. Lookup is a single read cycle, deterministic, no float, no multiply, no MAC array. Power per decision is orders of magnitude below TinyML inference on the same data.
L0 carries the joint row, L1 carries the running condition, L2 carries the asset identity. Three small CAM blocks compose the substrate’s descent shape on the die. Each level is a single read. No sequential model rollout, no recurrent state machine.
Embedded crypto on the same die signs the row before it leaves the analog domain. Chain-of-custody is established at the transducer, not at the host. Audit and regulatory regimes that depend on capture provenance gain a foundation they do not currently have.
Phase-change cells, ferroelectric RAM, or NOR flash sectors give the library the append-only property structurally. New rare-rows write once; existing rows are never modified. The substrate’s never-forget property holds without OS, without filesystem, without retraining.
Same multi-SKU composition shape as the other research directions. The substrate is the architecture; partner foundries supply the silicon.
Library-of-libraries lookup as a CAM read on the sensor die itself.
Sub-microsecond decision path from sample to signed output, on the same die.
Sealed kernel calls implemented as fixed CAM-indexed lookups, deterministic.
Per-die cryptographic identity. Every signed row attributable to a specific sensor.
Append-only on-die record store via phase-change cells or NOR sectors.
Host-side audit interface against on-die signed records.
Federated library updates via signed deltas; on-die receivers verify and append.
Per-die state isolation in multi-sensor systems.
Cascade-shape detection on-die for safety-critical sensor streams.
DARPA Microsystems Technology Office, NSF SemiSynBio + Future of Manufacturing, NIST CHIPS R&D, DOE Office of Science (sensors), ARPA-H (medical sensing).
MIT MTL, Stanford Nano, Berkeley BWRC, Imec, Fraunhofer IIS, ETH Zurich Integrated Systems, IMEC compute-in-memory groups.
Sensor IC and MEMS foundries (TSMC specialty, GlobalFoundries, X-FAB, SilTerra, TowerSemi), sensor system vendors (Bosch Sensortec, ST, TDK InvenSense, Analog Devices), compute-in-memory startups.
Validiti does not own a fab, will not design analog front ends, will not package or test silicon, and is not pursuing sensor IC manufacture as a commercial Marketplace SKU. The substrate-at-the-source-of-sampling architecture is research-mode work, published for the field, available for licensing to foundry and sensor partners and for research collaboration with labs and federal program offices.
Architectural argument, available on request to qualified semiconductor researchers, foundry partners, sensor IC vendors, and federal program affiliates. Preprint paper in preparation; will appear on arXiv and through sensors and integrated-systems research conferences. DARPA MTO concept paper in draft. Patent filings on the substrate-at-the-source architectural mapping in process.
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